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| Integrated Device Technology, Inc. 32K x 32 MCache SYNCHRONOUS PIPELINED CACHE RAM IDT71F432 FEATURES: Uses IDT's Fusion Memory technology 66 and 75 MHz speed grades 3-1-1-1 Pipelined Burst Read 3-1-1-1 Pipelined Burst Write 3-1-1-1-1-1-1-1... extended pipelined operation Refresh overhead consumes less than 0.5% of cycles Pinout is superset of industry standard PBSRAM Interchangeable with PBSRAM in new designs Compatible with MoSys MCacheTM devices Low operating and standby power consumption 1/3 the power of standard PBSRAM * Packaged in a JEDEC Standard 100-pin rectangular plastic thin quad flatpack (TQFP) * * * * * * * * * * DESCRIPTION: The IDT71F432 MCache is a high-performance, low-power replacement for standard 32K x 32 pipelined burst SRAM (PBSRAM) in cache applications. The 71F432 is built using IDT's Fusion Memory technology, which combines the performance of SRAM with the cost structure of DRAM. It is fundamentally compatible with standard PBSRAM, with additional features to accommodate the internal DRAM operation of the memory. These additional features are defined so that 71F432 compatible system controllers and properly implemented PC boards can work transparently with either the 71F432 or PBSRAM in cache memory applications. Six pins, identified as No Connect (NC) on the standard PBSRAM specifications, are used to support 71F432 operation. These pins are 5V supply (2), host bus W/R#, RESET# and two proprietary functions labeled F0 and F1. When using standard PBSRAM, these pins have no effect and the associated functions in the 71F432-compatible chipset are not activated. The 71F432 supports PBSRAM operating modes, including burst read (3-1-1-1), burst write (3-1-1-1) and pipelined burst read or write (3-1-1-1-1-1...). As with all DRAM devices, refresh is required. The memory is not accessible during the refresh interval. Refresh occupies 0.5% of the clock cycles, resulting in a system performance reduction of less than 0.1%. ABOUT IDT'S Fusion Memory TECHNOLOGY: What is Fusion Memory? * Fusion Memory is a new kind of memory technology that combines the high performance and ease-of-use of SRAM with the manufacturing costs of DRAM. Why are Fusion Memory chips so much smaller than SRAM? * Traditional SRAM uses four or six transistors to make each memory cell. Fusion Memory uses only one transistor for each memory cell, so the memory array itself is only about 1/4 the size of an SRAM. Is Fusion Memory the same as Dynamic Memory? * Not exactly. While both Fusion Memory and DRAMs use single-transistor dynamic cells for storage, Fusion Memories use much different designs for all the surrounding circuitry, such as address drivers, sense amps, and control circuitry. This gives Fusion Memory a performance level that is much higher than DRAM. If Fusion Memory uses dynamic storage, are there refresh cycles? * Yes, but the refresh control is handled automatically and nearly invisibly, using either on-chip circuitry or circuitry in the chip set used with the memory device. The performance penalty is typically less than 0.1%. How does the performance of Fusion Memory cache RAMs compare with synchronous burst SRAMS? * The Fusion Memory devices equal the performance of the SRAMs they are designed to replace. Are Fusion Memory and PBSRAMs interchangeable? * A system designed to use the Fusion Memory cache RAMs can use standard PBSRAMs instead. What is the difference between MoSys MCacheTM and IDT's Fusion Memory? * MCache is MoSys' trademark for their cache memory devices. Fusion Memory is IDT's trademark for the underlying technology. IDT will use the technology in other products besides cache RAMs. The IDT71F432 and MoSys' MCache devices are interchangeable. Fusion Memory SRAM Performance DRAM Cost Fusion MemoryTM Provides SRAM Performance at DRAM Cost The IDT logo is a registered trademark and Fusion Memory and CacheRAM are trademarks of Integrated Device Technology Pentium is a trademark of Intel Corp. MCache is a trademark of MoSys, Inc. COMMERCIAL TEMPERATURE RANGE (c)1996 Integrated Device Technology, Inc. DECEMBER 1996 DSC-3555/3 13.1 1 IDT71F432 32Kx32 MCache SYNCHRONOUS PIPELINED CACHE RAM COMMERCIAL TEMPERATURE RANGE 256KB CACHE BLOCK DIAGRAM PROCESSOR BUS CPU D[63:32] CPU ADS# CPU W/R# BE#[8:5] RESET# CPU A[17:3] CPU D[31:0] CPU ADS# CPU W/R# BE#[4:1] CPU A[17:3] TAG SRAM CHIPSET CACHE CONTROLLER CLK ADSC# CE# OE# ADV# GW# BWE# F0, F1 CS0 CS1# IDT71F432 32Kx32 RESET# IDT71F432 32Kx32 PIN DESCRIPTION SUMMARY SYMBOL A14 - A0 CE# CS0, CS1# OE# GW# BWE# BW1#, BW2#, BW3#, BW4# CLK ADV# ADSC# ADSP# I/O31-I/O0 DESCRIPTION Address Inputs Chip Enable Chip Selects Output Enable Global Write Enable Byte Write Enable Individual Byte Write Selects Clock Burst Address Advance Address Status (Cache Controller) Address Status (Processor) Data Input/Output TYPE Input Input Input Input Input Input Input Input Input Input Input I/O PIN NUMBER 48, 47, 46, 45, 44, 81, 82, 99, 100, 32, 33, 34, 35, 36, 37 98 97, 92 86 88 87 93, 94, 95, 96 89 83 85 84 29, 28, 25, 24, 23, 22, 19, 18, 13, 12, 9, 8, 7, 6, 3, 2, 79, 78, 75, 74, 73, 72, 69, 68, 63, 62, 59, 58, 57, 56, 53, 52 NC NC RESET# W/R# F0 F1 VDD5 VDD VSS Reserved for LBO# (burst order) Reserved for ZZ (sleep) Host Bus Reset Signal Host Bus W/R# Function 0 Function 1 5V Power 3.3V Power Ground NC NC Input Input Special Special Pwr Pwr Gnd 31 64 38 39 43 42 16, 66 4, 11, 15, 20, 27, 41, 54, 61, 65, 70, 77, 91 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 77 3555 tbl 01 13.1 2 IDT71F432 32Kx32 MCache SYNCHRONOUS PIPELINED CACHE RAM COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol VDD5 VDD VTERM TA TBIAS TSTG PT IOUT Rating VDD5 Voltage with Respect to VSS VDD Voltage with Respect to VSS Terminal Voltage with Respect to VSS Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Com'l. 0 to 5.5 0 to 3.6 -0.5 to VDD+0.5 0 to +70 -55 to +125 -55 to +125 1.0 20 Unit V V V C C C W mA RECOMMENDED DC OPERATING CONDITIONS Symbol VDD5 VDD VSS VIH VIL Parameter Supply Voltage Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.75 (1) Typ. 5.0 3.3 0 -- -- Max. 5.25 3.6 (1) Unit V V V (2,3) 3.135 0 2.0 -0.3 (4) 0 VDD+0.3 0.8 V V NOTES: 3555 tbl 03 1. Power sequencing. VDD5 must be VDD at all times, including during power up. 2. VIH (max.) must be observed at all times, including during power up. 3. VIH (max.) = VDD + 1.0V for pulse width less than tCYC/2, once per cycle. 4. VIL (min.) = -1.0V for pulse width less than tCYC/2, once per cycle. NOTE: 3555 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VDD = 3.3V +10/-5%, VDD5 = 5V 5%) Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Condition VDD = Max., VIN = 0V to VDD Outputs disabled, VOUT = 0V to VDD, VDD = Max. IOL = 5mA, VDD = Min. IOH = -5mA, VDD = Min. -- 2.4 0.4 -- V V 3555 tbl 04 Min. -- -- Max. 5 5 Unit A A DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1, 2) (VDD = 3.3V +10/-5%, VDD5 = 5V 5%) 71F432S66 71F432L66 5V 3.3V 5V 3.3V Supply Supply Supply Supply Unit 55 18 45 15 mA 35 10 30 2 25 1 mA 15 0.5 5 0.1 5 2 0.1 0.1 mA 3555 tbl 05 71F432S75 Symbol Parameter IDD Operating Supply Current Idle ISB Supply Current ISB1 Clock Stopped Supply Current Test Condition Device Selected, VIN VHD or VLD, Outputs Open, VDD = Max., VDD5 = Max., f = fMAX(3) Device Selected, ADSP#, ADSC#, GW#, BW#s, ADV# VHD, All Other Inputs VHD, Outputs Open, VDD, VDD5 = Max.,f = fMAX(3) VIN VHD, Outputs Open, VDD = Max., VDD5 = Max., f = 0(3) Power S L S L S L NOTES: 1. All values are maximum guaranteed values. 2. VHD = VDD - 0.2V, VLD = 0.2V 3. At f=fMAX,address inputs are cyclinng at maximum frequency of read cycles; f=0 means address input lines are changing. 13.1 3 IDT71F432 32Kx32 MCache SYNCHRONOUS PIPELINED CACHE RAM COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (VDD = 3.3V +10/-5%, TA = 0 to 70C) IDT71F432S75 Symbol tF tCYC tCH (1) IDT71F432S66 IDT71F432L66 Min. Max. -- 15 6 6 -- 2 0 2 -- 0 -- 2.5 1.5 7 -- -- 66.7 -- -- -- 7 -- -- 15 7 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 3555 tbl 06 Parameter Clock Frequency Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock High to Valid Data Clock High to Data Change Clock High to Output Active Clock High to Data High-Z Output Enable Access Time Output Enable Low to Data Active Output Enable High to Data High-Z Input Setup Time Input Hold Time Min. -- 13.3 5 5 -- 2 0 2 -- 0 -- 2.0 1.5 Max. 75 -- -- -- 6 -- -- 15 6 -- 6 -- -- Clock Parameters tCL(1) tCD tCDC tCLZ(2) tCHZ(2) tOE tOLZ(2) tOHZ tSxx tHxx (2) Output Parameters Set Up and Hold Times NOTES: 1. Measured as HIGH above 2.0V and LOW below 0.8V. 2. Transition is measured 200mV from steady-state. TIMING WAVEFORMS tCYC CLK tSxx All Inputs (except OE#) tCH tHxx tCL tCD tCLZ I/O[31:0] output tCDC tCHZ tOLZ tOE OE# tOHZ 13.1 4 IDT71F432 32Kx32 MCache SYNCHRONOUS PIPELINED CACHE RAM COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION CS0 BW4# BW3# BW2# BW1# CS1# VDD VSS CLK GW# BWE# OE# ADSC# ADSP# ADV# A8 A9 A6 A7 CE# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC I/O16 I/O17 VDD VSS I/O18 I/O19 I/O20 I/O21 VSS VDD I/O22 I/O23 NC VDD VDD5 VSS I/O24 I/O25 VDD VSS I/O26 I/O27 I/O28 I/O29 VSS VDD I/O30 I/O31 NC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 PK100-1 14mm x 20mm x 1.4mm body 1.6mm max total height 0.65mm pin pitch 63 62 61 60 59 58 57 56 55 54 53 52 51 NC I/O15 I/O14 VDD VSS I/O13 I/O12 I/O11 I/O10 VSS VDD I/O9 I/O8 VSS VDD5 VDD NC I/O7 I/O6 VDD VSS I/O5 I/O4 I/O3 I/O2 VSS VDD I/O1 I/O0 NC ORDERING INFORMATION IDT 71F432 Device Type X Power XX Speed PF Package 75 66 S L Speed in MHz NC A5 A4 A3 A2 A1 A0 RESET# W/R# VSS VDD F1 F0 A10 A11 A12 A13 A14 NC NC TOP VIEW TQFP Standard Power (66 and 75 MHz) Low Power (66 MHz only) 13.1 5 |
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